Description:
- Combines instructions together to run at once, packages them into “issue slots”
- 2-wide: 2 instructions per 1 cycle
- 4-wide: 4 instructions per 1 cycle
- Static Dual Issue: 2-wide
- Statically detected by compiler:
- Hardware doesnt detect and resolve hazards, Compiler must avoid hazards
- To avoid dependencies, for example 2-wide, only group 1 insn of ALU/branch/nop and 1 insn of Load/Store/nop.
- Then the 2nd instruction needs separate sign extend and a smaller ALU (only add/minus)
- Compiler must schedule to maximize Instruction per Cycle
Superscalar, Dynamic Scheduling:
- Dynamic multiple Issue
- CPU chooses multiple instructions to issue each cycle
- as CPU can have many processing units
- Compiler can help, by reordering instructions but CPU resolves hazards
- Scheduling is done at execution time
- Out-of-order Execution:
- Execute instructions as early as possible
- Guess results of branches, loads, etc.
- Roll back if guesses were wrong
- Don’t commit results until all previous instructions committed