Input Output Devices

Definition:

• Uses Interuption to tells processor to stop its processes and process the current input events (asynchronous) first

IO Controllers:

• I/O connected with I/O Controllers
  • high-performance interconnect: processor, memory, display
  • lower-performance interconnect: disk, keyboard, network
  • 

I/O Device API:

• Typical I/O Device API: a set of read-only or read/write registers
• Command registers: writing causes device to do something
• Status registers: reading indicates what device is doing, error codes, …
• Data registers
  • Write: transfer data to a device
  • Read: transfer data from a device

Communicating with a device:

Programmed I/O:

• special instructions talk over special busses. Specify: device, data, direction. example:
  • inb x1, 0x64 (reading keyboard status register)
  • outb x1, 0x60 (sending data to keyboard data register)
• Requires special instructions
• Can require dedicated hardward to interact with devices

char read_kbd()
{
	do{
	sleep();
	status = inb(0x64);
	} while(!(status & 1));
	return inb (0x60);
｝

Memory-mapped I/O:

• map registers into virtual address space, Virtual Memory
  • accesses to certain addresses redirected to I/O devices
  • data goes over the memory bus (faster!)
• Reuses standard load/store instructions and memory hardware interface

struct kbd  {
	char status; 
	char data;
}；
kbd *k = mmap (...);
char read_kbd()
{
	do {
		sleep();
		status = k->status;
	} while!(status & 1));
	return k->data;
}

Program check for status/data from device

Polling:

• Periodically check I/O status register
• Common in small, cheap, or real-time embedded systems (Predictable timing, inexpensive)
• Wastes CPU cycles

Interuption

• Device sends interrupt to CPU like in event-based
• Cause register identifies the interrupting device
• Interrupt handler examines device, decides what to do
  • Only interrupt when device ready/done
• Forced to save CPU context (PC, SP, registers, etc.)
• Unpredictable, event arrival depends on other devices’ activity

Path of communication from Processor to device:

Programmed:

• Device ←> CPU ←> RAM transfer
• for i = 1,…n:
  • CPU issues read request
  • Device puts data on bus then CPU reads into registers
  • CPU writes data to memory

DMA